The present invention relates to a semiconductor device, particularly relates to a semiconductor device in which a protection circuit for protecting from electrostatic discharge is built.
A device forming a semiconductor integrated circuit (IC) is minute and is easily broken by electrostatic discharge (ESD). Therefore, a protection circuit for protecting an internal circuit from electrostatic discharge caused outside is built in the semiconductor integrated circuit, and various ESD tests according to requests from users and others are made. As a static electricity applied model used in the ESD test, a human body model and a machine model are represented.
This type (the human body model and the machine model) of protection circuit ordinarily includes a protection circuit using a transistor or a protection circuit using a diode.
The protection circuit using a transistor and the protection circuit using a diode will be described below.
FIG. 11 is a circuit diagram showing the protection circuit using a field effect transistor.
The protection circuit 700 using the field effect transistor includes the field effect transistor 701 which is provided between a power supply terminal 703 for supplying power to an internal circuit 702 and an input/output terminal 704 for inputting/outputting a signal to/from the internal circuit 702. The drain of the field effect transistor 701 is connected to the power supply terminal 703. The source and the gate of the field effect transistor 701 are connected to the input/output terminal 704.
Owing to the configuration, when the potential of the input/output terminal 704 increases because of electrostatic discharge, the field effect transistor 701 is turned on to discharge electric charge caused by electrostatic discharge into the power supply terminal 703 so that the potential of the input/output terminal 704 is clamped.
FIG. 12 shows a characteristic of the protection circuit using the transistor and FIG. 13 show the voltage/current characteristics of the transistor and a diode. FIG. 13A shows the characteristic of voltage on a time base when a pulse is applied and FIG. 13B shows the characteristic of current on a time base when the pulse is applied.
FIGS. 12, 13A and 13B show the characteristics in case the transistor and the diode have the same size.
The impedance (Δ V1/Δ I1) of the transistor shown by a full line in FIG. 12 is smaller, compared with the impedance (Δ V2/Δ I2) of the diode shown by a broken line in FIG. 12. However, in the transistor 701, a characteristic represented by a curved full line in FIGS. 12 and 13A, that is, so-called snapback effect is caused. The rise time of current is delayed by τ because of the snapback effect as shown by a full line in FIG. 13B. Therefore, correspondence with respect to the input of ESD having a rising waveform of which is sharper than that in a human body model or a machine model for example is delayed, and the internal circuit and a protective device may be broken.
FIG. 14 is a circuit diagram showing the protection circuit using a diode.
The protection circuit 800 using a diode includes a diode 801 which is provided between a power supply terminal 803 and an input/output terminal 804. The cathode of the diode 801 is connected to the power supply terminal 803 and the anode of the diode 801 is connected to the input/output terminal 804.
Owing to the configuration, when the potential of the input/output terminal 804 increases because of electrostatic discharge, the diode 801 is turned on to discharge the electrostatic discharge into the power supply terminal 803 so that the input/output terminal 804 is clamped at predetermined potential.
FIG. 15 show characteristics of the protection circuit using the diode. FIG. 15A shows a characteristic of voltage on a time base when a pulse is applied and FIG. 15B shows a characteristic of current on the time base when the pulse is applied.
In the diode 801, voltage and current rise in response to an input pulse substantially at the same time as shown in FIG. 15. However, after the rise, impedance is increased as shown in FIG. 15A. Therefore, for protecting the internal circuit from the input of higher-voltage ESD than that in a human body model or a machine model, the device is required to be large-sized to reduce impedance.
In the above mentioned, for requests from users for ESD tests, there is a case that a test using a very higher-voltage and high-speed ESD pulse, compared with a human body model or a machine model is requested.
However, as first transition until a transistor is turned on is delayed by the above-mentioned snapback effect in case the above-mentioned test is made in a protection circuit using the transistor, a problem that the protection circuit cannot correspond to an ESD pulse the leading edge of which is sharp and an internal circuit may be broken occurs.
Also, in case the above-mentioned test is made in a protection circuit using a diode, the area of a device is required to be increased to reduce the impedance. Therefore, to correspond to a high-voltage ESD pulse, a problem that the device in which the protection circuit is to be mounted is large-sized occurs.